As is well known in the semiconductor art, a complementary MOS (CMOS) device comprises an interconnected P channel MOS (PMOS) transistor and N channel MOS (NMOS) transistor. Similarly, a complementary bipolar device incorporates an interconnected NPN transistor and PNP transistor. The desirability of monolithic structures which incorporate complementary MOS transistors, e.g. for a logic function, and complementary bipolar transistors, e.g. for power control, is well recognized as described, for example, in U.S. Pat. No. 3,865,649 issued Feb. 11, 1975 to Beasom entitled "Fabrication Of MOS Devices And Complementary BiPolar Transistor Devices In A Monolithic Substrate" and U.S. Pat. No. 4,299,024 issued Nov. 10, 1981 to Piotrowski entitled "Fabrication Of Complementary Bipolar Transistors And CMOS Devices With Poly Gates."
In certain device applications, such as those in which a "radiation hard" structure is needed, it is further desirable for the various transistors on a device to be effectively electrically isolated from one another, such as by an interposed layer of dielectric material. However, such conventional dielectrically isolated (DI) structures are typically very expensive to fabricate owning to an inherently low-yield fabrication process. In addition to the description in the previously cited references, conventional DI structure fabrication processes are described in U.S. Pat. No. 3,689,357 issued Sept. 5, 1972 to Jordan entitled "Glass-Polysilicon Dielectric Isolation" and U.S. Pat. No. 3,938,176 issued Feb. 10, 1976 to Sloan, Jr. entitled "Process For Fabricating Dielectrically Isolated Semiconductor Components Of An Integrated Circuit." Basically, dielectric isolation processing involves the steps of (a) forming grooves in a monocrystalline silicon wafer; (b) forming an oxide dielectric layer on the wafer surface so as to coat the grooves; (c) depositing a thick (e.g. 250 microns) polycrystalline layer on the grooved wafer surface so as to provide a "handle" for further processing; (d) lapping the back side of the original wafer so as to expose the oxide covered grooves; and (e) forming transistors in the monocrystalline silicon "tubs" between the grooves.
This cumbersome conventional process is inefficient, expensive, and of low yield for a variety of reasons, including wafer warpage and crystalline defect density. Wafer warpage limits the diameter of processable wafers and routinely causes unacceptably wide deviations in flatness over relatively short distances on the wafer surface, in turn creating insurmountable photolithographic problems. Crystalline defects are induced in the dielectrically isolated tubs of silicon by virtue of the significant stress created by the polysilicon deposition and further impact device yield.
In an effort to overcome the very significant contraints of conventional DI device processing, the present invention was conceived.